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应俊,朱云鹏.基于CORDIC矩阵奇异值分解的FPGA实现[J].重庆邮电大学学报(自然科学版),2020,32(3):434-440. 本文二维码信息
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基于CORDIC矩阵奇异值分解的FPGA实现
FPGA implementation of matrix singular value decomposition based on CORDIC
投稿时间:2018-12-24  修订日期:2019-12-16
DOI: 10.3979/j.issn.1673-825X.2020.03.013
中文关键词:  奇异值分解  现场可编程门阵列  单边雅克比变换
English Keywords:singular value decomposition  field programmable gate array  one-sided Jacobi
基金项目:国家自然科学基金(61771082,61871062,61801065)
作者单位E-mail
应俊 重庆邮电大学 光电工程学院,重庆 400065
重庆邮电大学 光通信与网络重点实验室,重庆 400065 
yingjun@cqupt.edu.cn 
朱云鹏 重庆邮电大学 光电工程学院,重庆 400065
重庆邮电大学 光通信与网络重点实验室,重庆 400065 
yunpeng_zhu@foxmail.com 
摘要点击次数: 76
全文下载次数: 43
中文摘要:
      在矩阵的奇异值分解(singular value decomposition,SVD)过程中,随着矩阵维数的增加,SVD的计算量呈指数型增长,从而降低了算法运行的实时性。针对这个问题,基于Hestenes-Jacobi数值计算方法,提出了一种改进的基于坐标旋转数字计算机(coordinate rotation digital computer,CORDIC)的逻辑设计,该逻辑设计采用并行的全流水线设计思想,能够提高Jacobi平面旋转变换的运行速度,进而加快任意维矩阵奇异值分解的计算速度。分析了基于Hestenes-Jacobi方法的SVD的数值计算过程,介绍了CORDIC算法的基本原理,并具体说明了基于CORDIC算法的Jacobi平面旋转模块的设计,利用Verilog语言实现设计并验证,在现场可编程门阵列(field-programmable gate array,FPGA)上运行该逻辑设计单元,与Matlab软件的运行结果进行对比。实验测试结果表明,该结构能够减少计算时间,适应高速数据处理的要求。
English Summary:
      In singular value decomposition (SVD) of a matrix, the matrix dimension increases along with the exponential increase in the computational complexity of SVD; that reduces the real-time performance of the algorithm. To alleviate this issue, this paper proposes an improved logic design for the coordinate rotation digital computer (CORDIC) based on the Hestenes-Jacobi numerical calculation method. The logic design adopts the parallel full pipeline design idea that improves the running speed of the Jacobi plane rotation transformation. Therefore, to accelerate the computational speed of singular value decomposition of an arbitrary dimensional matrix; this paper first analyzes the numerical calculation process of SVD based on Hestenes-Jacobi method, then introduces the basic principle of CORDIC algorithm, and specifies the design of Jacobi plane rotation module based on CORDIC algorithm. Furthermore, it also uses Verilog language to realize the design and verification of the logic. To validate the concept the logic design unit is implemented on the field programmable gate array (FPGA) and Matlab toolkit. The experimental test results show that the structure can reduce the calculation time and meet the requirements of high-speed data processing.
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